The following is an article regarding my experience trying to build better tooling for `Digital Design`, using `Rust`. I'll be covering the challenges I've faced in trying to build new tooling and my experience with `Rust` along the way.
1. Iterative Level-Based Evaluation
### Motivation
I'll give some quick background on what led me down this rabbit hole (and spoiler it goes deep). I majored in Computer Science and minored in Electrical Engineering. My favorite class in school was `COP 4020: Programming Language Concepts` which is essentially a portion of a compiler course. However, I got heavily involved with my minor as well and ended up loving a different class `EEL 4712: Digital Design`. This course covered the tools and techniques used to design digital circuits. It's an extension of `Digital Logic` that focuses on using an `RTL` language to create *synthesizable* circuits. Fast forward 6 years and I've been working as a software engineer in my industry. Despite software being my first love, I always missed playing with `Digital Design` because it felt unique in that it was a lot like software development but could manifest itself to something you could physically touch. I wanted to at least gain the skills back that I lost from when I would create circuits back in undergrad. I re-visited the tooling I used to use and was stunned! The tooling felt archaic, and lagging behind the tools used by my software cohorts. That's when it hit me, maybe I can help change that. Alas, I found that there is a *reason* these tools feel outdated. It's because EDA software represents decades of development effort and is unlike a lot of software that gets released and adopted rapidly in the world of software development, especially in the web development world. It turns out that the challenges underlying the tooling within an EDA suite, actually is much closer to a computer science problem than an electrical/hardware problem! Some of the topics I've encountered include graph theory, compiler design, systems programming concepts, and more. From there I was hooked! This is a great problem space to work on your fundamental computer science skills while solving and potentially contributing towards a unique space.
### Rust
For no reason in particular, I chose Rust to work on this project, which presented me with it's own series of challenges but I found the best way to learn a language is to build with it and at the time Rust was the language I was most interested in learning. Particularly because I was interested in its systems programming capabilities, which *could* prove useful later in the project.
### My First Stab
It's worth noting that back at this point I did not know precisely what I would be building. I thought maybe I'd be building a drag and drop visual logic gate editor. However, I wanted to see if I could make a higher impact project and also selfishly the thought of making a drag and drop canvas type of program sounded difficult because I'm definitely no UI specialist.
The reason I bring that up is that because of that early choice in what I was building, one choice has lingered long into my development and depending on how you view it could be a good or bad thing.
### The `.hdl`Format
The original way I would describe a circuit in my first version would be something like this
```rust
//Create gates (connected only to power and ground)
let gate0 = circuit.add_gate(GateType::AND, GateId::power(), GateId::ground());
// Create a gate with one input from power/ground and the other from another gate
let gate1 = circuit.add_gate(GateType::OR, gate0, GateId::power());
//Create a gate with two inputs both from other gates
circuit.add_gate(GateType::AND, gate1, gate0);
//Evaluate the circuit
circuit.evaluate();
```
As you can imagine, this imperative approach grew quickly out of control given that I had to instantiate every gate and later had to wire up every connection manually.
Enter the `.hdl` format. This is an easy to use file format with an associated HDL that you can use to describe your circuit declaratively with a very easy to understand syntax. It was created for the [nand2teris](https://www.nand2tetris.org/) course (which is great btw) as an educational tool to help guide students in understanding how logic gates construct the hardware we use in our computers.
```hdl
CHIP Circuit {
IN a, b;
OUT out;
PARTS:
And(a=a, b=b, out=out1);
Or(a=out1, b=a, out=out2);
And(a=out2, b=out1, out=out);
}
```
I chose this format because it seemed infinitely easier to parse and reason about than a full fledged HDL language like `vhdl` and this helped me represent the circuit I wanted to evaluate easily. After all, I was more focused on the evaluation algorithm rather than parsing at this time.
... more coming on this post ✍🏻